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19 March 2007  
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Home - Technology - Article

Tech Primer


The stratospheric growth in the processing power of computers has only intensified the age old problem of CPU utilisation. CPU vendors are thus looking for a higher speed RAM, to counter this problem. Apart from speed, size is also an important factor while look out for an alternative. While eDRAM faces competition from other alternatives in terms of speed, its smaller size makes it a more viable option.

What is eDRAM?

Embedded dynamic random access memory is commonly known as embedded DRAM or simply eDRAM. eDRAM is a capacitor-based dynamic random access memory usually integrated on the same die or in the same package as the main ASIC or microprocessor, as opposed to external DRAM modules and transistor-based static random access memory (SRAM) typically used for caches.

Designed for on-die use with CPUs, eDRAM is nearly as fast as the SRAM currently used for on-die CPU caches, but uses far less processor real estate—about half as much in some cases.

While DRAM is quite well known, it’s not suitable for use with CPUs due to its relatively high latencies. The much-faster SRAM has proven its utility for on-die cache, but uses a lot of die space. IBM’s POWER6 CPU will sport 8 MB of L2 SRAM cache, which will take up a lot of room. IBM says that it has a 65 nm prototype eDRAM, running with 1.5 ns latency and 2 ns random cycle time. These speeds are competitive with current SRAM.

IBM’s new eDRAM, designed in stress-enabled 65nm silicon-on-insulator (SOI) using deep trench, improves on-processor memory performance in about one-third the space consuming one-fifth the standby power of conventional SRAM (static random access memory), which allows you to put more cache memory inside the chip or lower the costs of a processor.


Embedding large blocks of DRAM into an ASIC brings many advantages. By eliminating the need to drive I/O signals to separate memory chips, eDRAM boosts memory performance and overall system bandwidth. Eliminating the I/O drivers also reduces power consumption and noise. ASIC pin counts and PCB layers decrease as well, often allowing the use of a smaller, less expensive ASIC package and PCB. A smaller package and reduced component count can simplify board layouts, allowing you to shrink the size of your board.

The advanced structure dramatically reduces parasitic resistance and capacitance throughout the memory array, thus minimising both random access time and power consumption. The low parasitics also ensure stable operation under low operating voltage, as required for today’s CMOS logic.

Embedding permits much wider buses and higher operating speeds, and due to the much higher density of DRAM in comparison to SRAM, larger amounts of memory can potentially be used. However, the difference in manufacturing processes makes on-die integration difficult, so several dies have to be packaged in one chip, raising costs. The latest developments overcome this limitation by using the standard CMOS process to manufacture eDRAM, as in 1T-SRAM.

eDRAM in action

eDRAM is already being used in many game consoles, including the Sony PS2 and PlayStation Portable, Nintendo Wii and GameCube, and Microsoft Xbox 360. Both the Cell CPU used in the PlayStation 3 and the IBM POWER CPUs will utilise eDRAM for L2 cache, likely in IBM’s 45 nm process node.

—Varun Aggarwal

For further information, visit:www.ibm.com/press/us/en/pressrelease/21074.wss


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